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Address-Sharing Method for Half-Good Random-Access Memory Chips

IP.com Disclosure Number: IPCOM000062362D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Fitzgerald, BF: AUTHOR [+2]

Abstract

A method of addressing is described which makes possible the use of any good 2 of 4 arrays on partial good 4-array memory chips as well as all the arrays on an all-good 4-array chip. The method requires that each chip be provided with a sectional compare circuit. By this means, a large reduction is realized in the number of chip categories. Thus, the number of chip sorts and required substrate types is reduced substantially. In memory chips having four sections or memory arrays, each array has identical row-column decoding so that the same address is selected in each array. High-order address bits control a specialized decoder that selects one of the 4 arrays, allowing that array to clock data to the data output circuitry. The decoder selects one of the 4 arrays of an all-good chip.

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Address-Sharing Method for Half-Good Random-Access Memory Chips

A method of addressing is described which makes possible the use of any good 2 of 4 arrays on partial good 4-array memory chips as well as all the arrays on an all-good 4-array chip. The method requires that each chip be provided with a sectional compare circuit. By this means, a large reduction is realized in the number of chip categories. Thus, the number of chip sorts and required substrate types is reduced substantially. In memory chips having four sections or memory arrays, each array has identical row-column decoding so that the same address is selected in each array. High-order address bits control a specialized decoder that selects one of the 4 arrays, allowing that array to clock data to the data output circuitry. The decoder selects one of the 4 arrays of an all-good chip. In the case of a 1/2-good chip, the decoder drops out the highest-order address bit and shifts the electrical address of the good arrays to the lowest 1/2 of the address positions. Thus, any combination of 2 good arrays will constitute a 1/2- good chip, and all combinations have the high-order address dropped out. Implementation of this 1/2-good chip method in an eight-module package requires the on-chip logic shown in the figure. Three binary addresses chip sar1, chip sar2, and chip sar3 are used to select one chip within that module. Each of the eight chip locations within that module biases three programming pads p1, p2, p3 uniquely, as determined by binary count. All chips within the module c...