Browse Prior Art Database

CMOS Frequency Divider

IP.com Disclosure Number: IPCOM000062369D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Dutta, S: AUTHOR

Abstract

A frequency divide circuit using CMOS technology can be implemented to generate latch and trigger clocks. Only one oscillator is needed to generate the clock signals. The circuit can be efficiently designed in a CMOS VLSI environment. By utilizing a minimum number of devices, the circuit offers silicon area saving and higher operating speed when compared with the traditional CMOS frequency. A widely used CMOS frequency divider circuit is shown in Fig. 1(A) and its block diagram is shown in Fig. 1(B). The circuit configuration is based on the master-slave principle. The circuit shows a master flip-flop formed from two inverters and a feedback device TG2, as well as a transfer gate TG1 that feeds a slave flip-flop having a similar arrangement. The Q output is returned to the data input.

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CMOS Frequency Divider

A frequency divide circuit using CMOS technology can be implemented to generate latch and trigger clocks. Only one oscillator is needed to generate the clock signals. The circuit can be efficiently designed in a CMOS VLSI environment. By utilizing a minimum number of devices, the circuit offers silicon area saving and higher operating speed when compared with the traditional CMOS frequency. A widely used CMOS frequency divider circuit is shown in Fig. 1(A) and its block diagram is shown in Fig. 1(B). The circuit configuration is based on the master-slave principle. The circuit shows a master flip-flop formed from two inverters and a feedback device TG2, as well as a transfer gate TG1 that feeds a slave flip-flop having a similar arrangement. The Q output is returned to the data input. Both the oscillator and inverted oscillator are required to control the transfer gates. A total of 20 devices are required for this circuit. A new CMOS frequency divide circuit is shown in Fig. 2. Only the oscillator is required to control the transfer gates (the inverted oscillator is not required). The circuit performs the same operation as Fig. 1. When the oscillator is low (logic '0'), the transfer gate TG5 is closed and the TG6 is open. This allows the master flip-flop to sample incoming data and the slave to hold data from a previous input and feed it to the output. When the oscillator is high, the TG5 is open and the TG6 is closed, so that the master ho...