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CMOS Toggle Flip-Flop

IP.com Disclosure Number: IPCOM000062377D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Carlile, PS: AUTHOR

Abstract

A CMOS toggle flip-flop circuit design is presented which uses less than one-half the number of devices used in a conventional toggle flip-flop. A static edge-triggered flip-flop design is shown in Fig. 1 and a timing chart for the circuit is shown in Fig. 2. The circuit can be initiated by either pulsing the CLEAR line or the PRESET line while CLOCK is low, depending on the polarity of output initially desired. By pulsing the CLEAR line, T17 is turned on and output Q (node E) is pulled down. When node E is pulled down, T13 turns on, T14 turns off and node F goes high. With CLOCK low and not CLOCK high, pass devices T1 and T2 and T9 and T10 are set off and pass devices T7 and T8 and T15 and T16 are set on. When devices T15 and T16 are on, output data line not Q (node D) is pulled high.

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CMOS Toggle Flip-Flop

A CMOS toggle flip-flop circuit design is presented which uses less than one- half the number of devices used in a conventional toggle flip-flop. A static edge- triggered flip-flop design is shown in Fig. 1 and a timing chart for the circuit is shown in Fig. 2. The circuit can be initiated by either pulsing the CLEAR line or the PRESET line while CLOCK is low, depending on the polarity of output initially desired. By pulsing the CLEAR line, T17 is turned on and output Q (node E) is pulled down. When node E is pulled down, T13 turns on, T14 turns off and node F goes high. With CLOCK low and not CLOCK high, pass devices T1 and T2 and T9 and T10 are set off and pass devices T7 and T8 and T15 and T16 are set on. When devices T15 and T16 are on, output data line not Q (node D) is pulled high. The output levels of data lines Q and not Q are held in flip-flop T11, T12, T13 and T14. With CLOCK line low, not CLOCK line high and pass devices T7 and T8 on, the complementary output (not Q) is passed to node A. When CLOCK line rises, pass devices T1 and T2 and T9 and T10 turn on while pass devices T7 and T8 and T15 and T16 turn off. Pass devices T1 and T2 turning on cause the data at node A to be latched in flip-flop T3, T4, T5, and T6. Node A is isolated from node D (output not Q) by T7 and T8 going off and the flip-flop T11, T12, T13 and T14 output is disabled by T15 and T16 being turned off. Node D (output not
Q), driven by pass gates T9 and T10, is s...