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Up and Down Siliciding Process Patterned by Utilizing a Lift-Off Process

IP.com Disclosure Number: IPCOM000062387D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Koburger, CW: AUTHOR [+3]

Abstract

A lift-off process is used to pattern silicon over a blanket layer of refractory metal so that self-aligned silicide interconnect regions can be formed in a CMOS transistor. To form a silicide, which is a compound of silicon and a refractory metal, the constituent elements must intermix through an annealing process. When polycrystalline silicon lies above the refractory metal, the silicide is formed by a down-diffusion of the silicon into the refractory metal film. Conversely, when the polysilicon lies below the refractory metal, a silicide is formed by up-diffusion of silicon into the refractory metal film. Here, a lift-off technique is used to define conductive silicide interconnect lines between diffusions without the use of an insulating film or a contact mask. Since the diffusions (i.e.

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Up and Down Siliciding Process Patterned by Utilizing a Lift-Off Process

A lift-off process is used to pattern silicon over a blanket layer of refractory metal so that self-aligned silicide interconnect regions can be formed in a CMOS transistor. To form a silicide, which is a compound of silicon and a refractory metal, the constituent elements must intermix through an annealing process. When polycrystalline silicon lies above the refractory metal, the silicide is formed by a down-diffusion of the silicon into the refractory metal film. Conversely, when the polysilicon lies below the refractory metal, a silicide is formed by up-diffusion of silicon into the refractory metal film. Here, a lift-off technique is used to define conductive silicide interconnect lines between diffusions without the use of an insulating film or a contact mask. Since the diffusions (i.e., regions of doped monocrystalline silicon) react to form silicides at the same rate as the polysilicon interconnect, and since there is no contact border, the alignment tolerance of the interconnect mask to prior levels is increased. Fig. 1 shows a cross-section of a CMOS transistor structure 10. A blanket layer of refractory metal 11 is deposited, and a "cold deposited" polysilicon film 12 is evaporated through a lift-off mask (not shown) atop the refractory metal 11. The polysilicon film 12 is used to define the metal interconnects over silicon dioxide regions 13. Note that the lift-off process poses n...