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Selective Word Transfer on Cross-Interrogation Castouts

IP.com Disclosure Number: IPCOM000062396D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

In a MP system whose CPUs have a store in cache algorithm, a cache line whose contents have been stored into by the CPU contains the only copy of the data for the MP system. In the event a second CPU requires access to the data, the line must be transferred from the first to the second CPU. In some present systems this is done over a separate "line castout bus". The requesting CPU initiates a request to main memory for the line and the storage control unit (SCU) fields this request and activates both a request to main memory and an interrogation of the other CPU's cache contents. If the line is in the other CPU's cache and modified, then the request to main memory is cancelled and the line is transferred via the "line castout bus," one doubleword (DW) per cycle. This takes 16 cycles for a typical system.

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Selective Word Transfer on Cross-Interrogation Castouts

In a MP system whose CPUs have a store in cache algorithm, a cache line whose contents have been stored into by the CPU contains the only copy of the data for the MP system. In the event a second CPU requires access to the data, the line must be transferred from the first to the second CPU. In some present systems this is done over a separate "line castout bus". The requesting CPU initiates a request to main memory for the line and the storage control unit (SCU) fields this request and activates both a request to main memory and an interrogation of the other CPU's cache contents. If the line is in the other CPU's cache and modified, then the request to main memory is cancelled and the line is transferred via the "line castout bus," one doubleword (DW) per cycle. This takes 16 cycles for a typical system. The present approach provides a method for the modifying CPU to remember which DWs within a cache line have been modified, and to only "cast-out" the modified words to the requesting CPU. The requesting CPU will not have the main memory access cancelled on a cross-interrogated cast-out, but will accept all words from memory, replacing only those that have been cast-out by the modifying CPU. The figure shows an implementation of the present approach. When one or more DW sections of a cache line are modified, a bit is turned on for each DW section modified in the "DW modified array" which contains 512 words, e...