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Dynamic Random-Access Memory Sense Amplifier Latch Set Circuit

IP.com Disclosure Number: IPCOM000062397D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Nickel, DJ: AUTHOR

Abstract

A dynamic random-access memory (DRAM) sense amplifier (SA) latch set circuit optimizes latch set time to insure maximum signal amplification, and the mechanism is self regulating. When a latch set pulse for a DRAM sense amplifier latch circuit is turned on too soon, the signal will be lost in the DRAM. If the latch set pulse is too late, time will be lost. By introducing an interlock feature to the SA latch set mechanism, the DRAM SA latch set pulse timing will be optimized. Shown in the figure is a schematic of a SA data latch set circuit 20, data latches 21 and a SA node X line which is common to the bottom of data latches 21 and a data latch's set monitor transistor Tx. The function of the SA latch set circuit is to discharge the heavily loaded SA node X line in a precisely controlled two-step sequence.

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Dynamic Random-Access Memory Sense Amplifier Latch Set Circuit

A dynamic random-access memory (DRAM) sense amplifier (SA) latch set circuit optimizes latch set time to insure maximum signal amplification, and the mechanism is self regulating. When a latch set pulse for a DRAM sense amplifier latch circuit is turned on too soon, the signal will be lost in the DRAM. If the latch set pulse is too late, time will be lost. By introducing an interlock feature to the SA latch set mechanism, the DRAM SA latch set pulse timing will be optimized. Shown in the figure is a schematic of a SA data latch set circuit 20, data latches 21 and a SA node X line which is common to the bottom of data latches 21 and a data latch's set monitor transistor Tx. The function of the SA latch set circuit is to discharge the heavily loaded SA node X line in a precisely controlled two-step sequence. Node X is pulled down slowly at first to give more time for signal amplification and to prepare the latches 21 for a precise set time. Secondly, node X is pulled all the way down to ground extremely fast under control of latch set monitor Tx to latch the data on the bit lines (BL) at maximum signal amplitude. The automatic two-step sequence for controlling SA node X insures optimum latch set conditions every time a data latch is set. To implement a two- step latch set sequence, Tx must have geometric characteristics resulting in performance specifications which are identical to latch devices A1 and A2. This is done by orienting device Tx and the latch devices on the same axis so that all device characteristics, such as threshold voltage VT, match as closely as possible. The size of the devices in the SA latch set circuit 20 is also important. Tz is large, Ty is small, Tx is very small and T2, T4, T6, T8 and T10 are normal- ...