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Triple Fault-Masking Redundancy Logic Circuits for Bipolar and FET Application

IP.com Disclosure Number: IPCOM000062400D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Wang, WY: AUTHOR

Abstract

Triple fault-masking redundancy logic circuits may be employed in bipolar and FET applications to obtain improved performance over existing dual fault-masking redundancy with respect to reductions in metal shorting and unwanted noise capacitive coupling on chip. The logic redundancy representation of triple fault-masking logic is illustrated in Fig. 1. Circuit implementation of a triple redundancy error-correcting switching function Fx0 is shown in Fig. 2. The truth table of such an error-correcting output is shown in Table 1. The outputs from such error-correcting circuits provide fault-masking majority logic. If inter-level metal shorts have not occurred in the multi- level metallization process, the center line x1 can either be physically shorted to lines x0 or x2, or metal 'open'.

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Triple Fault-Masking Redundancy Logic Circuits for Bipolar and FET Application

Triple fault-masking redundancy logic circuits may be employed in bipolar and FET applications to obtain improved performance over existing dual fault- masking redundancy with respect to reductions in metal shorting and unwanted noise capacitive coupling on chip. The logic redundancy representation of triple fault-masking logic is illustrated in Fig. 1. Circuit implementation of a triple redundancy error-correcting switching function Fx0 is shown in Fig. 2. The truth table of such an error-correcting output is shown in Table 1. The outputs from such error-correcting circuits provide fault-masking majority logic. If inter-level metal shorts have not occurred in the multi- level metallization process, the center line x1 can either be physically shorted to lines x0 or x2, or metal 'open'. In such a case, the center error-correcting output will always be in the correct Boolean state (except last case and third case ('open') with the inter- level metal short in Table 1.) This center line error-correcting output can go directly to the next stage Boolean switching without XT0 or XT2 connecting to its gates. XT1 will be the faster of the three error-correcting outputs if either x0 or x2 are shorted to some other metal lines. The error-correcting switching function requires two- level logic to correct single faults. The Boolean switching function after error- correcting output can be either a N...