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High Resolution Enhancement for an On-Chip Variable Strobe-Timing Generator

IP.com Disclosure Number: IPCOM000062405D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Kaczmarczyk, JM: AUTHOR [+2]

Abstract

An enhancement is proposed to a technique to simplify the external timing requirements for high performance arrays used in semiconductor bipolar gate arrays. An improved logic/layout design is proposed which offers multiple selectable paths with identical logic blocks that have various capacitive loads yielding delay differences less than a logic block delay. In a previous work [*] a technique was developed to measure the access time of high performance embedded arrays. This used an on-chip variable strobe-timing generator with one technology block delay resolution. This proposal enhances the design so that the resolution of the variable clock strobe is less than one technology block delay. A diagram of the proposed circuit which will increase the resolution of the variable clock strobe is given in Fig. 1.

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High Resolution Enhancement for an On-Chip Variable Strobe-Timing Generator

An enhancement is proposed to a technique to simplify the external timing requirements for high performance arrays used in semiconductor bipolar gate arrays. An improved logic/layout design is proposed which offers multiple selectable paths with identical logic blocks that have various capacitive loads yielding delay differences less than a logic block delay. In a previous work [*] a technique was developed to measure the access time of high performance embedded arrays. This used an on-chip variable strobe-timing generator with one technology block delay resolution. This proposal enhances the design so that the resolution of the variable clock strobe is less than one technology block delay. A diagram of the proposed circuit which will increase the resolution of the variable clock strobe is given in Fig. 1. It is an enhancement of the circuit in Fig. 2, which is that proposed in [*]. In that reference the variable clock strobe is the D-OUT clock, which will also be used in this discussion. However, the variable clock may be extended to all clocks (ADDR-IN, DATA-IN, R/W). The new circuit shown in Fig. 1 is obtained by taking the +TG D-OUT clock from Fig. 2 and connecting it to point I in Fig. 1. The driver for the -TG D-OUT clock should also be removed from Fig. 2. With this modification of the Fig. 1 circuit, the delay added to the +TG D-OUT clock is: W (delay added to +TG D-OUT CLK) = 2X technology block delays delay due to CN Therefore, by properly choosing...