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Word Line Detector Circuit

IP.com Disclosure Number: IPCOM000062414D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Ellis, W: AUTHOR [+3]

Abstract

This article describes a random-access memory (RAM) circuit which optimizes the timing between word line select and signal amplification. Conventional methods of selecting a sense amplifier (S/A) at the appropriate time after the word line (WL) select rely on a word line delay compensation circuit to accommodate the worst-case cell delay or a sample word line circuit to simulate (track) the rise time of the actual word line. An ideal method of selecting a S/A for optimum performance is to use the actual physical word line (PWL) or reference word line (RWL) to trigger the S/A timing clocks. The use of a RWL for tracking rather than a WL is preferred because the number of RWLs is substantially less than that of the actual WLs. One RWL and one WL in a cell array will be driven high at a time.

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Word Line Detector Circuit

This article describes a random-access memory (RAM) circuit which optimizes the timing between word line select and signal amplification. Conventional methods of selecting a sense amplifier (S/A) at the appropriate time after the word line (WL) select rely on a word line delay compensation circuit to accommodate the worst-case cell delay or a sample word line circuit to simulate (track) the rise time of the actual word line. An ideal method of selecting a S/A for optimum performance is to use the actual physical word line (PWL) or reference word line (RWL) to trigger the S/A timing clocks. The use of a RWL for tracking rather than a WL is preferred because the number of RWLs is substantially less than that of the actual WLs. One RWL and one WL in a cell array will be driven high at a time. Because the Word Line Detector circuit must OR together these WLs or RWLs to receive a signal to trigger the S/A timing, the Word Line Detector circuit will be more lightly loaded, resulting in a higher performance with less area impact if the RWL option were selected. Fig. 1 shows the generalized concept of a Word Line Detector circuit 10 physically located at the end of the RWLs 11. Optimum access will be realized by placing the detector circuit 10 at the terminal end of the RWLs 11. A S/A bit line (BL) will be activated when a RWL rises to a predetermined level, triggering the S/A timing clocks. Fig. 2 shows the Word Line Detector circuit which may...