Browse Prior Art Database

Chip Leveling During Solder Reflow

IP.com Disclosure Number: IPCOM000062417D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Bosley, RC: AUTHOR [+4]

Abstract

A method and fixture are described for assuring level chip-to-substrate positioning during and after the solder reflow process step of face- down semiconductor circuit chip bonding to a next wiring level, e.g., a ceramic substrate chip carrier. Referring to the figure, semiconductor device chip 2 is first placed in position on a ceramic substrate chip carrier 4 and held in position by means of a paste solder flux. Several chips are usually thus attached to several ceramic substrates which are held in a fixture (not shown) for transport during the reflow operation. Chip leveling weight 6 is brought into contact with the back (top) of chip 2 by means of leveling weight carrier 8.

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Chip Leveling During Solder Reflow

A method and fixture are described for assuring level chip-to-substrate positioning during and after the solder reflow process step of face- down semiconductor circuit chip bonding to a next wiring level, e.g., a ceramic substrate chip carrier. Referring to the figure, semiconductor device chip 2 is first placed in position on a ceramic substrate chip carrier 4 and held in position by means of a paste solder flux. Several chips are usually thus attached to several ceramic substrates which are held in a fixture (not shown) for transport during the reflow operation. Chip leveling weight 6 is brought into contact with the back (top) of chip 2 by means of leveling weight carrier 8. The leveling weight carrier 8 is aligned and attached to the substrate transport fixture by means of friction clips (also not shown) which assure that the vertical members of leveling carrier 8 are in contact with the top surface of ceramic substrate 4. This reflow assembly of chip 2 on ceramic substrate 4 with leveling weight 6 applying pressure on chip 4 is then subjected to oven temperature sufficient to melt solder pads 14. Leveling weight 6 drops to the position shown, limited in its motion downward by leveling weight spacer pins 16, thus assuring parallelism and fixed spacing between the plane of the back of chip 2 and the plane of the top surface of ceramic substrate
4. Note that leveling weight support pin 10 is only in contact with locating notch...