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Programmable, High Speed, 50-Ohm, Pulse Driver

IP.com Disclosure Number: IPCOM000062421D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Blaisdell, CW: AUTHOR [+4]

Abstract

A multi-level pulse driver is described which is useful in semiconductor device testing. This driver features the ability to pre-program a continuous train of pulses each of which may have a different predetermined voltage level anywhere between the limits of +5.5 and -5.5 volts at cycle times of less than 20 nanoseconds. The driver has a 50-ohm output impedance and a 10-nanosecond delay from input to output. The driver incorporates manual time skew adjustment on leading and trailing edges of pulses for precise delay and width alignment between drivers. Referring to the figure, information-defining pulse voltage levels are stored in random-access memories (RAMs) A and C. RAM A and RAM C are addressed via line 4 and data is transferred from Ram A to latch B or Ram C to latch D by means of select lines 1 and 2, respectively.

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Programmable, High Speed, 50-Ohm, Pulse Driver

A multi-level pulse driver is described which is useful in semiconductor device testing. This driver features the ability to pre-program a continuous train of pulses each of which may have a different predetermined voltage level anywhere between the limits of +5.5 and -5.5 volts at cycle times of less than 20 nanoseconds. The driver has a 50-ohm output impedance and a 10-nanosecond delay from input to output. The driver incorporates manual time skew adjustment on leading and trailing edges of pulses for precise delay and width alignment between drivers. Referring to the figure, information-defining pulse voltage levels are stored in random-access memories (RAMs) A and C. RAM A and RAM C are addressed via line 4 and data is transferred from Ram A to latch B or Ram C to latch D by means of select lines 1 and 2, respectively. An input pulse IN switches multiplexer E to select data from latch B or D for transmission to digital- to-analog converter (DAC) F. DAC F produces a voltage level to amplifier G for amplification to output OUT through a 50-ohm coaxial cable. Timing skew adjustment is performed on input pulses via manually variable resistor R1. Resistors R2 and R3 are loads for the DAC F. The resistor R4 provides input damping for an amplifier G. A manually variable capacitor C provides voltage waveform shaping capability. A resistor R5 having a value of 50 ohms can be placed in series with the coaxial cable and the...