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PC BIOS Performance Enhancements for Non-Pc Supported Display Adapters

IP.com Disclosure Number: IPCOM000062437D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Krishnamurty, R: AUTHOR [+3]

Abstract

By setting up in Basic Input/Output System (BIOS) Random-Access Memory (RAM) a mailbox data area for communication between BIOS and coprocessor Virtual Resource Manager (VRM) display code, non-PC supported display adapters can be utilized without having to accept a major performance degradation for the total emulation of all the video BIOS commands. A hardware base consisting of a high speed Reduced Instruction Set Computer (RISC) microcomputer with an IBM PC AT (Advanced Technology) compatible I/O bus is provided with compatibility with IBM PC applications by supporting the Intel 80286 coprocessor. The 80286 coprocessor support code in the VRM must emulate PC monochrome and color adapters onto non-PC supported display adapters.

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PC BIOS Performance Enhancements for Non-Pc Supported Display Adapters

By setting up in Basic Input/Output System (BIOS) Random-Access Memory (RAM) a mailbox data area for communication between BIOS and coprocessor Virtual Resource Manager (VRM) display code, non-PC supported display adapters can be utilized without having to accept a major performance degradation for the total emulation of all the video BIOS commands. A hardware base consisting of a high speed Reduced Instruction Set Computer (RISC) microcomputer with an IBM PC AT (Advanced Technology) compatible I/O bus is provided with compatibility with IBM PC applications by supporting the Intel 80286 coprocessor. The 80286 coprocessor support code in the VRM must emulate PC monochrome and color adapters onto non-PC supported display adapters. There are video BIOS entry points which are called frequently by PC applications and cause many I/O interrupts to be handled by the coprocessor display support code and the coprocessor card trap logic. The monitoring and emulating of all these interrupts degrade the screen update performance considerably. The solution to this problem is to set up a mailbox data area in BIOS RAM for communication between BIOS and coprocessor VRM display code. There are mainly two video BIOS entry points which degrade screen update performance. One is the "set cursor position" command, and the other is the "scroll" command. Video BIOS code was modified to pass informational parameters in the mailbox data area, generate an interrupt, and then wait for a status bit to be cleared, to flag the finish of the emulating of that video command. For "set cursor position", BIOS performs a...