Browse Prior Art Database

Defect Skip Algorithm

IP.com Disclosure Number: IPCOM000062458D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Ouchi, NK: AUTHOR

Abstract

A method is described for using hardware to locate disk surface defects utilizing previously recorded defect information, comprising the steps of (1) storing defect locations of a track into a memory array, (2) comparing each upcoming cell location with the next defective cell location from the memory array, and (3) if there is a match, inserting a defect skip. The use of hardware to locate disk surface defects obviates the need for computations required in conventional methods. The figure shows an implementation of the method. Defective cell locations are extracted from the count and home address fields of a track and are stored successively in memory array 1. The current cell location is also extracted from the count and home address fields of a track and is stored in register 2.

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Defect Skip Algorithm

A method is described for using hardware to locate disk surface defects utilizing previously recorded defect information, comprising the steps of (1) storing defect locations of a track into a memory array, (2) comparing each upcoming cell location with the next defective cell location from the memory array, and (3) if there is a match, inserting a defect skip. The use of hardware to locate disk surface defects obviates the need for computations required in conventional methods. The figure shows an implementation of the method. Defective cell locations are extracted from the count and home address fields of a track and are stored successively in memory array 1. The current cell location is also extracted from the count and home address fields of a track and is stored in register 2. The content of register 2 is initially incremented twice so that it contains a cell location which is two cells ahead of the current cell location. It is subsequently incremented with each crossing of a cell boundary. The next defective cell location is transferred from memory array 1 into register 3 where it is compared with the content of register 2 by means of compare logic 4. A match condition in compare logic 4, which indicates a surface defect two cells ahead, is input into a two- stage shift register 5, which is subsequently shifted at each subsequent cell crossing. The output from 5a thus indicates that the next cell is defective, while the output from 5b...