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Best Solution Generator for Redundancy

IP.com Disclosure Number: IPCOM000062467D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Koch, GS: AUTHOR

Abstract

This article relates to a technique for selecting the best replacement lines for faulty row and column lines in a two-dimensional redundant semiconductor memory array. Possible solutions for repairing random-access memories (RAMs) that are designed with spare rows and columns can be very large and illusive as the redundancy increases. Software algorithms that find most or all solutions for assigning replacement rows and columns in place of faulty ones are slow and the repair time is a function of the number of spares used. Once the best replacements have been chosen, the memory locations of the faulty lines are relocated in redundant columns or rows.

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Best Solution Generator for Redundancy

This article relates to a technique for selecting the best replacement lines for faulty row and column lines in a two-dimensional redundant semiconductor memory array. Possible solutions for repairing random-access memories (RAMs) that are designed with spare rows and columns can be very large and illusive as the redundancy increases. Software algorithms that find most or all solutions for assigning replacement rows and columns in place of faulty ones are slow and the repair time is a function of the number of spares used. Once the best replacements have been chosen, the memory locations of the faulty lines are relocated in redundant columns or rows. With a limited number of word and bit line replacements available, the selection process must be rigorous and find the best combination of replacement lines to use when the number of faulty lines exceeds the number of available redundant word or bit lines. A primary concept in the technique of selecting replacement lines for faulty rows or columns is called must-fix. The repair analysis process locates must-fix lines by scanning through the bit failure map. One axis of the bit failure map is designated as the scan axis, and the other axis is designated as the step axis. Lines in one direction are scanned, and the number of failures on that line are computed. If the number exceeds the number of redundant lines still remaining in the orthogonal direction, the scanned line is a must-fix so that it is immediately replaced. Once all the lines have been scanned in one direction, the lines in the orthogonal direction are similarly scanned. If any scan produces one or more must-fix lines, the scan must be repeated in the orthogonal direction. Every time a row or column is designated must-fix, the axis designations need to be changed at the completion of finding all must-fix lines in that dimension since the use of a spare row or column changes the criteria for a must-fix in the orthogonal direction. In order to reduce the lengthy scanning time required to locate and choose appropriate fixes, a hardware mask technique is used. By using a reduced fail map and a binary representation of the must-fix rows and columns as input masks for all possible repair solutions to one axis of the fail matrix, the remaining fails can be checked for repair by the detection RAMs on the other axis. The figure shows a flow diagram of the best solution generator. Oscillator 1 generates clock signals and feeds them into the counter 2 which generates consecutive addresses for the X fix pattern generator 3. Generator 3 is preloaded for each new device type to precondition logic 5 and contains all possible combinations of fixes on the X axis for a 4 x 4 (4 spare rows and 4 spare columns) redundancy. RAM 3 also contains a three-bit count of the number of X repair lines used for each possible repair solution. An address range of 6,196 is needed to contain all combinations of 0, 1, 2...