Browse Prior Art Database

Fabrication of a Sub-Minimum Lithography Trench

IP.com Disclosure Number: IPCOM000062469D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Davis, A: AUTHOR

Abstract

This article relates to a means of shrinking a trench image size below lithographic minimums by using spacer technology and lateral oxidation techniques. Sub-minimum geometry trenches for cell charge storage can be fabricated without increasing cell size or using multi-level resist (MLR) techniques which require additional masks. Fig. 1 shows a base structure used to fabricate a sub-minimum cell storage trench image. A film of nitride followed by a thick layer of silicon dioxide (SiO2) is deposited on a silicon substrate. A coat of photoresist (not shown) is applied on top of the SiO2 layer and imaged at or near minimum geometries. Fig. 2 shows the structure after a selective reactive ion etch (RIE) of the SiO2 down to the nitride surface. Fig.

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Fabrication of a Sub-Minimum Lithography Trench

This article relates to a means of shrinking a trench image size below lithographic minimums by using spacer technology and lateral oxidation techniques. Sub-minimum geometry trenches for cell charge storage can be fabricated without increasing cell size or using multi-level resist (MLR) techniques which require additional masks. Fig. 1 shows a base structure used to fabricate a sub-minimum cell storage trench image. A film of nitride followed by a thick layer of silicon dioxide (SiO2) is deposited on a silicon substrate. A coat of photoresist (not shown) is applied on top of the SiO2 layer and imaged at or near minimum geometries. Fig. 2 shows the structure after a selective reactive ion etch (RIE) of the SiO2 down to the nitride surface. Fig. 3 shows the structure after a chemical vapor deposition (CVD) of polysilicon which is used to shrink the dimensions of the etched groove. Sidewall spacers are formed next by a selective RIE down to the nitride layer, as shown in Fig. 4. The spacers are thoroughly oxidized before a RIE is used to open the exposed nitride down to the silicon substrate, as shown in Fig. 5. The trench, shown in Fig. 6, is fabricated by utilizing a selective RIE process which etches the silicon substrate at a much faster rate than the silicon dioxide on top of the structure. The same technique described for fabricating sub- minimum lithographic images for trenches used to store charge can be utili...