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Dynamic Burn-In of Integrated Circuit Chips at the Wafer Level

IP.com Disclosure Number: IPCOM000062472D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

DeLuca, BF: AUTHOR [+2]

Abstract

By fabricating a wafer with special test circuitry in the kerf area which is driven by conductor lines extending to pads around the perimeter of a wafer, each chip on the wafer is dynamically burned-in prior to wafer dicing. Integrated circuits (ICs) shipped to customers in the unmounted chip format benefit from a technique which allows for burn-in at the wafer level prior to dicing as well as a cost-saving technique over module burn-in methods. The kerf area between the active chips is utilized to fabricate test circuitry. Counters and voltage toggling circuits are used to dynamically exercise chip inputs. Each chip and its test circuitry are driven through conductors extending to pads located around the perimeter of a wafer. Power lines have multiple pads on the wafer perimeter to carry the load currents required.

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Dynamic Burn-In of Integrated Circuit Chips at the Wafer Level

By fabricating a wafer with special test circuitry in the kerf area which is driven by conductor lines extending to pads around the perimeter of a wafer, each chip on the wafer is dynamically burned-in prior to wafer dicing. Integrated circuits (ICs) shipped to customers in the unmounted chip format benefit from a technique which allows for burn-in at the wafer level prior to dicing as well as a cost-saving technique over module burn-in methods. The kerf area between the active chips is utilized to fabricate test circuitry. Counters and voltage toggling circuits are used to dynamically exercise chip inputs. Each chip and its test circuitry are driven through conductors extending to pads located around the perimeter of a wafer. Power lines have multiple pads on the wafer perimeter to carry the load currents required. A printed circuit board (PCB) appropriately wired and fabricated with a circular hole slightly smaller than a wafer diameter is used as a wafer-mounting means. The PCB pad configuration around the perimeter of the hole matches the wafer pad configuration around the edge of the wafer and the PCB is attached to the wafer with a radiant heat source. A hole in the PCB insures chip pads do not contact anything which will damage the pads during a burn-in procedure. The PCB with a wafer attached is mounted in a controlled environmental chamber, and burn-in voltage is applied. After burn-in is com...