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# Model for Delta-I Correction

IP.com Disclosure Number: IPCOM000062473D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 33K

IBM

## Related People

Hickson, JB: AUTHOR [+4]

## Abstract

This article describes a method for correcting current distribution in some types of electrical networks. The method is applicable to the design of many types of integrated circuit chips, wafers, cards, boards and other electrical packages. The basic problem addressed is often known by the name "Delta-I". Assume some purely resistive electrical network is embedded in an integrated circuit chip design, with all current sources external to the chip and beyond the boundaries of the network. Standard equations can be used to evaluate the currents flowing in all branches of the network. Some of these currents may be considered "excessive", or beyond some desired limit. The chip wiring design can be modified to increase resistance within specific branches of the network. Where resistance is increased, the current is decreased.

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Model for Delta-I Correction

This article describes a method for correcting current distribution in some types of electrical networks. The method is applicable to the design of many types of integrated circuit chips, wafers, cards, boards and other electrical packages. The basic problem addressed is often known by the name "Delta-I". Assume some purely resistive electrical network is embedded in an integrated circuit chip design, with all current sources external to the chip and beyond the boundaries of the network. Standard equations can be used to evaluate the currents flowing in all branches of the network. Some of these currents may be considered "excessive", or beyond some desired limit. The chip wiring design can be modified to increase resistance within specific branches of the network. Where resistance is increased, the current is decreased. By iterative application of this method, currents of all branches can be brought within the desired limits. Modification of the design is done by local transformations of the wires. Fig. 1 shows an example of one type of transformation. In this example, the wire segment between points labeled "A" and "B" in Fig. 1A has been identified as one which would have too much current. To correct this situation, the design is changed to that shown in Fig. 1B. The total length of wire in this portion of the network is increased. Resistance increases linearly with wire length. As resistance increases, the current decreases linearly. The exact amount of the increase in wire length is determined by the amount of the desired decrease in current. Another type of transformation takes advantage of the differing electrical characteristics of the different kinds of network elements available on some types of chips. For example, diffusion regions can be used for connections which have resistances (typically) greater than comparable lengths of "metal" wire. Many chip designs contain areas where diffusion is not normally present. In these regions it is easy to transform a portion of the network design, as shown in Fig. 2. Fig. 2A includes the wire segment between points labeled "C" and "D" which has been identified as one which would have too much current. Fig. 2B shows a portion of this segment replaced by an equal length of diffusion plus connections bet...