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Optimized Logic Layout Using SGP Technology

IP.com Disclosure Number: IPCOM000062482D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Bechade, RA: AUTHOR

Abstract

Utilization of horizontal and vertical metal lines to interconnect internal nodes of logic functions will enhance circuit layout densities in the silicon gate process (SGP). The layout of any two-level logic function in the SGP technology can be optimized where the first level of logic is composed of more than one adjacent logic block and the second level of logic is a function of the first level logic blocks. The internal nodes of the first level logic blocks can be connected with vertical metal lines (first level metal), and the internal nodes of the second level logic can be connected with horizontal metal lines (second level metal). Fig. 1 shows a two-level random logic block diagram with inputs A through H, and Fig. 2 shows a physical layout of the logic block diagram.

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Optimized Logic Layout Using SGP Technology

Utilization of horizontal and vertical metal lines to interconnect internal nodes of logic functions will enhance circuit layout densities in the silicon gate process (SGP). The layout of any two-level logic function in the SGP technology can be optimized where the first level of logic is composed of more than one adjacent logic block and the second level of logic is a function of the first level logic blocks. The internal nodes of the first level logic blocks can be connected with vertical metal lines (first level metal), and the internal nodes of the second level logic can be connected with horizontal metal lines (second level metal). Fig. 1 shows a two-level random logic block diagram with inputs A through H, and Fig. 2 shows a physical layout of the logic block diagram. This layout uses horizontal polysilicon input lines (A through H) which intersect orthogonal channels (0 through 7). Each of the seven logic block output devices is placed in a different vertical channel (1-7) and the outputs are used to form a seven-way NOR function in channel 0. Internal first level logic nodes (i.e., ground, output and VDD) in the channels (1-7) are connected together by utilizing first level metal lines located above the channels (1-7). Each of the seven logic blocks is terminated in a output load device (i.e., 1L through 7L), and the output nodes are brought out to the left side of the layout utilizing horizontal polysilicon lines. Note that this layout utilizes an additional channel (0) on the le...