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FET Decoder Tree Layout for Speed Improvement

IP.com Disclosure Number: IPCOM000062484D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Houghton, RJ: AUTHOR

Abstract

This article relates to a FET (field-effect transistor) decoder circuit design allowing a layout technique in silicon which enhances the capacitive drive output capability without additional input drive requirements or silicon area. Improved speed through additional drive capability with no additional silicon required for layout can be realized when a tree-style arrangement of FET decoder devices is used rather than a conventional NAND approach. Fig. 1a shows a conventional NAND decoder. Fig. 1b is the physical layout of the NAND devices in silicon. A diffusion region 10 is associated with each device source/drain, and a device gate 11 is associated with each address input, i.e., A0, A0 not, A1, A1 not,...etc. All levels of the serial-connected devices, shown in Fig. 1a, have a gate width of W.

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FET Decoder Tree Layout for Speed Improvement

This article relates to a FET (field-effect transistor) decoder circuit design allowing a layout technique in silicon which enhances the capacitive drive output capability without additional input drive requirements or silicon area. Improved speed through additional drive capability with no additional silicon required for layout can be realized when a tree-style arrangement of FET decoder devices is used rather than a conventional NAND approach. Fig. 1a shows a conventional NAND decoder. Fig. 1b is the physical layout of the NAND devices in silicon. A diffusion region 10 is associated with each device source/drain, and a device gate 11 is associated with each address input, i.e., A0, A0 not, A1, A1 not,...etc. All levels of the serial-connected devices, shown in Fig. 1a, have a gate width of
W. The approximate effective gate width for the NAND decoder in silicon (Fig. 1b) is WNAND = W/N, where N is the number of levels in the serial chain. Fig. 2a shows a decoder tree which is a logical equivalent to the NAND decoder in Fig. 1a. Devices T1A, T1B,...etc. at the top of the decoder tree have a gate width of W as in the NAND decoder. Devices at the next level down in the decoder tree have a gate width of 2W, and gates at the third level down have a width of 4W. Thus, the gate widths at each level in the tree are made approximately twice as large as the level above. The top level of the decoder tree layout, as shown in Fig. 2b, is identical to the NAND layout in Fig. 1b. Diffusion 20 is associated with the drain of device T1A and diffusion 21 is associated with the drain of T1B. The schematic (Fig. 2a) shows a common source for devices T1A and T1B which is tied to the drain of device T2A at the next level down in the tre...