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Half Supply Voltage (1/2 Vdd) Bitline, With a Wordline Boost After Sense, in CMOS DRAM Circuits

IP.com Disclosure Number: IPCOM000062487D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Davis, A: AUTHOR

Abstract

Dynamic random-access memory (DRAM) circuits are improved by combining a word line boost after the sense cycle with 1/2 Vdd operation of bit lines. Reliability is improved, a full signal level is stored, and the benefit of reduced power dissipation is retained. Complementary metal-oxide-silicon (CMOS) sense amplifiers permit setting 2 bit lines in a DRAM at 1/2 Vdd, and the data is sensed as a variation of one bitline from a mid-point between the two. Some DRAM array designs provide a marginal signal, and the word line is raised above Vdd (boosted or bootstrapped) to store a full Vdd level in a cell. By providing this word line boost at the right time, just after the sense cycle, a full Vdd level is stored. During the read cycle a transfer device is turned on by application of Vdd only.

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Half Supply Voltage (1/2 Vdd) Bitline, With a Wordline Boost After Sense, in CMOS DRAM Circuits

Dynamic random-access memory (DRAM) circuits are improved by combining a word line boost after the sense cycle with 1/2 Vdd operation of bit lines. Reliability is improved, a full signal level is stored, and the benefit of reduced power dissipation is retained. Complementary metal-oxide-silicon (CMOS) sense amplifiers permit setting 2 bit lines in a DRAM at 1/2 Vdd, and the data is sensed as a variation of one bitline from a mid-point between the two. Some DRAM array designs provide a marginal signal, and the word line is raised above Vdd (boosted or bootstrapped) to store a full Vdd level in a cell. By providing this word line boost at the right time, just after the sense cycle, a full Vdd level is stored. During the read cycle a transfer device is turned on by application of Vdd only. The transfer device stays on since the bit line is at 1/2 Vdd, a full level was stored, and the bit line never moves to within a voltage threshold (Vt) of the gate voltage. Thus, the advantages of a word line boost are present though the word line (gate) is only at Vdd.

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