Browse Prior Art Database

Method for Minimizing Within-Chip Registration Error

IP.com Disclosure Number: IPCOM000062489D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Farrell, TR: AUTHOR

Abstract

A method is described for minimizing within-chip overlay errors when a mix of stepping reduction photo exposure tools (P1) and one-to-one scanning photo exposure tools (P2) are used in semiconductor circuit fabrication. This method uses capabilities already incorporated in P1 and P2 tools to compensate for magnification and skew overlay differences found to exist within-chip images formed by the two tools. First, the amount and sign of magnification difference is determined. The error is then compensated by adding an appropriate increment (of sign opposite to that of the magnification error) to the P1 step magnitude in both horizontal and vertical directions.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 99% of the total text.

Page 1 of 1

Method for Minimizing Within-Chip Registration Error

A method is described for minimizing within-chip overlay errors when a mix of stepping reduction photo exposure tools (P1) and one-to-one scanning photo exposure tools (P2) are used in semiconductor circuit fabrication. This method uses capabilities already incorporated in P1 and P2 tools to compensate for magnification and skew overlay differences found to exist within-chip images formed by the two tools. First, the amount and sign of magnification difference is determined. The error is then compensated by adding an appropriate increment (of sign opposite to that of the magnification error) to the P1 step magnitude in both horizontal and vertical directions. When the P2 tool is used to align to a P1 image, magnification of the P2 tool adjusts for over-all wafer alignment and, in so doing, now matches the P1 image at the chip level. An angular difference (skew) between individual chip images from the two tool types is corrected similarly by alteration of stepping increments in vertical and horizontal directions by unequal amounts to result in correct angular alignment at the chip level when P2 over-all wafer alignment is performed. After corrected stepping dimensions are programmed into the P1 tool, optimum overlay is achieved within chips for P1 to P2 or P2 to P1 image alignments. Stepping dimension corrections should be determined for each P1 tool used in a manufacturing line for best within-chip alignment to...