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Incremental Analysis of Circuit Electrical Response Simulation

IP.com Disclosure Number: IPCOM000062494D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Hsieh, HY: AUTHOR [+3]

Abstract

In simulation analysis of circuits, a minimum number of outputs, from which all other outputs can be computed, e.g., all the node voltage waveforms, are saved. Thus, it becomes possible to extract detailed information incrementally at a later date without having to repeat a complete transient electrical simulation of the circuit. It is currently common practice to request many more outputs than are needed from a circuit simulation to try to avoid a complete rerun for a detail not originally requested. The new technique of storing all node voltage waveforms initially saves computer time. Incremental analysis for details as need arises requires minimal additional computer time. For example, source-drain current of a field-effect transistor (FET) in a circuit may be calculated from previously stored node voltage waveforms, e.g.

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Incremental Analysis of Circuit Electrical Response Simulation

In simulation analysis of circuits, a minimum number of outputs, from which all other outputs can be computed, e.g., all the node voltage waveforms, are saved. Thus, it becomes possible to extract detailed information incrementally at a later date without having to repeat a complete transient electrical simulation of the circuit. It is currently common practice to request many more outputs than are needed from a circuit simulation to try to avoid a complete rerun for a detail not originally requested. The new technique of storing all node voltage waveforms initially saves computer time. Incremental analysis for details as need arises requires minimal additional computer time. For example, source-drain current of a field-effect transistor (FET) in a circuit may be calculated from previously stored node voltage waveforms, e.g., waveforms at gate, source, substrate, and drain nodes of the FET. In reanalysis of a circuit after a minor change, only those nodal waveforms affected by the change need be recalculated by using stored waveforms upstream of the change. This technique has become possible with the advent of simulation methods in which circuits are decoupled and simulated in a modular fashion while still maintaining accuracy. Such a method is described in "Waveform Relaxation Method For Time Domain Analysis of Large Scale Integrated Circuits" by E. Lelarasmee, A. E. Ruehli, and A. L. Sangioranni- Vi...