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P-Well Charge Pump With Enhanced Reliability for High Voltage Chip Stressing

IP.com Disclosure Number: IPCOM000062499D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+2]

Abstract

By the addition of two devices to a standard P-well charge pump circuit, excessive voltage stressing of vulnerable devices in the circuit is avoided during high voltage stress tests. Referring to the figure, oscillator 2 connected with charge pump driver 4 feeds the charge pump circuit comprised of transistors T1, T2, T3, T4, and T5. Enhancement mode transistor T5 and low threshold voltage (low Vt) transistor T1 are added to a standard charge pump circuit comprised of transistors T2, T3, and T4. Furthermore, in the standard charge pump design, the gate of low Vt transistor T3 is connected to a phase that is high (at Vdd) when node OUT is at its negative potential. In the enhanced design, transistor T3 becomes gated by ground such that transistor T3 turns on when OUT drops to low Vt (0.7 volt) below ground.

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P-Well Charge Pump With Enhanced Reliability for High Voltage Chip Stressing

By the addition of two devices to a standard P-well charge pump circuit, excessive voltage stressing of vulnerable devices in the circuit is avoided during high voltage stress tests. Referring to the figure, oscillator 2 connected with charge pump driver 4 feeds the charge pump circuit comprised of transistors T1, T2, T3, T4, and T5. Enhancement mode transistor T5 and low threshold voltage (low Vt) transistor T1 are added to a standard charge pump circuit comprised of transistors T2, T3, and T4. Furthermore, in the standard charge pump design, the gate of low Vt transistor T3 is connected to a phase that is high (at Vdd) when node OUT is at its negative potential. In the enhanced design, transistor T3 becomes gated by ground such that transistor T3 turns on when OUT drops to low Vt (0.7 volt) below ground. Enhancement mode transistor T5 ensures that enhancement mode transistor T4 does not conduct ground current before transistor T3 turns on. Transistor T3 turns off transistor T4. Transistor T1 ensures that no device in the circuit can have more than supply voltage Vdd across a gate-source junction. Thus, transient high voltage (11 to 13 volts) previously impressed across gate-source junctions of transistors T2 and T3 during stress testing is avoided.

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