Browse Prior Art Database

Static Random-Access Memory Cell

IP.com Disclosure Number: IPCOM000062502D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Roberts, AL: AUTHOR [+2]

Abstract

A static four-device random-access memory (RAM) cell layout is described in which adjacent cell-pairs are symmetrical about a vertical axis and each cell has electrical and rotational symmetry about a central point. Separated placement of bit lines reduces capacitance between bit lines, thus increasing signal and performance of the cell. Another performance improvement is achieved by incorporating split word lines in the layout. Buried contacts are placed in the layout such that their contact resistance is in series with gates only, not with active current paths. This cell provides wiring to carry supply voltage Vdd to polysilicon load resistors. Thus, a mask level and an ion implantation process step usually required to form polysilicon connecting lines between Vdd and polysilicon load resistors are avoided. Fig.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 75% of the total text.

Page 1 of 2

Static Random-Access Memory Cell

A static four-device random-access memory (RAM) cell layout is described in which adjacent cell-pairs are symmetrical about a vertical axis and each cell has electrical and rotational symmetry about a central point. Separated placement of bit lines reduces capacitance between bit lines, thus increasing signal and performance of the cell. Another performance improvement is achieved by incorporating split word lines in the layout. Buried contacts are placed in the layout such that their contact resistance is in series with gates only, not with active current paths. This cell provides wiring to carry supply voltage Vdd to polysilicon load resistors. Thus, a mask level and an ion implantation process step usually required to form polysilicon connecting lines between Vdd and polysilicon load resistors are avoided. Fig. 1 is a layout diagram of a pair of four- device cells. Fig. 2 is a circuit diagram of one of the four-device cells. Identification numbers are located in the gate region of the four transistors T1, T2, T3, T4 in the left hand cell of Fig. 1. Each cell is associated with five parallel metal M lines which provide, in sequence Vdd, bit line BL, ground GND, bit line complement BLN, and another line Vdd which is shared with an adjacent cell. A pair of first level polysilicon P1 to substrate (through recessed oxide ROX) buried contacts BC is placed so as not to be in series with internal nodes. Split word lines WL provide acce...