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SRAM Cell Stability Enhancement Via DRAM Technology

IP.com Disclosure Number: IPCOM000062505D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Houghton, RJ: AUTHOR [+2]

Abstract

This article concerns the use of dynamic random-access memory (DRAM) charge-storage technology for the unique purpose of increasing static random-access memory (SRAM) cross-coupled cell node capacitance and thereby increasing cell stability to protect against data loss due to alpha particle radiation. 2 p. The need for storage node capacitance enhancements is ever increasing since high SRAM densities cause cell stability reductions, making the cell more susceptible to soft errors. Generally SRAM technology advances have reduced cell area and consequently reduced the charge stored on a cell's internal nodes. Fig. 1 shows a schematic of a typical cross-coupled SRAM cell structure with its parasitic capacitance at nodal points A and B.

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SRAM Cell Stability Enhancement Via DRAM Technology

This article concerns the use of dynamic random-access memory (DRAM) charge-storage technology for the unique purpose of increasing static random- access memory (SRAM) cross-coupled cell node capacitance and thereby increasing cell stability to protect against data loss due to alpha particle radiation. 2 p. The need for storage node capacitance enhancements is ever increasing since high SRAM densities cause cell stability reductions, making the cell more susceptible to soft errors. Generally SRAM technology advances have reduced cell area and consequently reduced the charge stored on a cell's internal nodes. Fig. 1 shows a schematic of a typical cross-coupled SRAM cell structure with its parasitic capacitance at nodal points A and B. Charge stored on the internal node of a typical cell is approximately 60 fc at a supply voltage of 3.4 volts and is in the region of error exposure due to alpha particle radiation. Fig. 2 shows a physical layout of the storage cell in Fig. 1 with enhanced internal capacitance at nodes A and B through the utilization of DRAM technology employing a trench for increased storage capacity. In this trench technology example, the node capacitance at A and B is about 120 ff compared to 10 ff for a typical SRAM cell layout without enhanced nodes. There is no additional cell area overhead for the trench enhancement but simply a process feature (trench) added. By utilizing a trench storage cap...