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Mosfet on Chip Timer Utilizing Device Conduction Near Threshold for Long Delay

IP.com Disclosure Number: IPCOM000062507D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Cranford, HC: AUTHOR [+2]

Abstract

This article describes an on-chip timer circuit which provides a pulse train with fairly long down-time (example: approximately 1 millisecond) and fairly short up-time. The circuit is fabricated from enhancement- and depletion-type FETs (field-effect transistors). The circuit utilizes device conductance in the near threshold region to obtain long timing intervals between pulses. In this region, only a very small amount of current is needed to provide a long discharge time. With reference to the figure, the output is a pulse train at node X9 which follows (that is, controlled by) node TX9. The small currents are generated by biasing the gates of devices 15 and 20 slightly above their respective threshold voltages (Vth).

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Mosfet on Chip Timer Utilizing Device Conduction Near Threshold for Long Delay

This article describes an on-chip timer circuit which provides a pulse train with fairly long down-time (example: approximately 1 millisecond) and fairly short up- time. The circuit is fabricated from enhancement- and depletion-type FETs (field- effect transistors). The circuit utilizes device conductance in the near threshold region to obtain long timing intervals between pulses. In this region, only a very small amount of current is needed to provide a long discharge time. With reference to the figure, the output is a pulse train at node X9 which follows (that is, controlled by) node TX9. The small currents are generated by biasing the gates of devices 15 and 20 slightly above their respective threshold voltages (Vth). The difference in discharge times between node A and node F is caused by the different bias voltages set by transistors 16, 17, 21 and 22. Node F is biased closer to the Vth of device 25 than is node A to device 9. Thus, less time is taken for the gate of device 25 to decay to a point near its threshold voltage. The delay is long because the current path is taken through a long device whose Vgs is barely above its Vth. This phenomenon may be stated mathematically as follows: Id V Vgs - Vth It should be noted that the current through 20 or 15 becomes quite small near the end of a discharge cycle. Moreover, with each voltage decrement, the current decrease is exponential...