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ITERATION Synchronization Architecture

IP.com Disclosure Number: IPCOM000062514D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Brady, JT: AUTHOR

Abstract

In machine architectures capable of supporting multiple simultaneous execution of successive iterations of a loop, there is a requirement that an iteration can communicate with the prior iteration and subsequent iterations relative to the state of shared resources. The efficiency of this communication has a substantial impact on the number of applications that can run on such machines. Each instruction in a machine instruction set contains a field to specify the synchronization requirement and to set or test the state of synchronization. ITERATION SYNCHRONIZATION: CMD = 1XX SYNCH CMD CMD = X1X HOLD CMD = XX1 RELEASE CMD = 1XX indicates that the loop contains dependencies on previous iterations. This is coded in the first instruction of the loop. The dependency is on the common registers and index registers.

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ITERATION Synchronization Architecture

In machine architectures capable of supporting multiple simultaneous execution of successive iterations of a loop, there is a requirement that an iteration can communicate with the prior iteration and subsequent iterations relative to the state of shared resources. The efficiency of this communication has a substantial impact on the number of applications that can run on such machines.

Each instruction in a machine instruction set contains a field to specify the synchronization requirement and to set or test the state of synchronization. ITERATION SYNCHRONIZATION: CMD = 1XX SYNCH CMD CMD = X1X HOLD

CMD = XX1 RELEASE CMD = 1XX indicates that the loop contains dependencies on previous iterations. This is coded in the first instruction of the loop. The dependency is on the common registers and index registers. Any reference to storage via a private resource is allowed to proceed. A fetch from a common register is blocked when the facility is in use, unless the previous iterations have completed or issued a RELEASE. The instruction where the dependency starts has an X1X in this field. The instruction where the dependency is satisfied has an XX1 in the field. The SYNCH indicates that subsequent iterations cannot access the common registers or use the common index registers after passing the HOLD until all the previous iterations have completed or issued the corresponding RELEASE. The first instruction of a loop codes the SYNCH if...