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Hardware-Assisted Test and Set Function

IP.com Disclosure Number: IPCOM000062522D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Miller, EW: AUTHOR [+3]

Abstract

This article describes a hardware-assisted Test and Set function which can improve the performance of multiprogramming or multiprocessor systems. The instruction sets for some microprocessors include a "test and Set (TAS) instruction which is used to coordinate control between two or more processors or between two or more programs being executed in a multiprogramming environment. This instruction reads a memory location determined by the effective address specified, tests the contents of that memory location, sets condition codes based upon the results of the test, and then writes back into the original memory specified. Two tests are applied to the contents of the specified memory location. One determines if the data's value is equal to zero.

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Hardware-Assisted Test and Set Function

This article describes a hardware-assisted Test and Set function which can improve the performance of multiprogramming or multiprocessor systems. The instruction sets for some microprocessors include a "test and Set (TAS) instruction which is used to coordinate control between two or more processors or between two or more programs being executed in a multiprogramming environment. This instruction reads a memory location determined by the effective address specified, tests the contents of that memory location, sets condition codes based upon the results of the test, and then writes back into the original memory specified. Two tests are applied to the contents of the specified memory location. One determines if the data's value is equal to zero. The other test examines only the most significant bit and sets a condition code accordingly. The original data is re-written back into the specified memory location except for the most significant bit which is always written back as a "one". The instruction requires two indivisible memory cycles--one to read the memory location specified and one to write back the original data with the most significant bit forced to "one". This means that memory access by all other devices is precluded for two memory cycles plus the time required for the tests on the data read. Performance requirements in some multiprocessor systems cannot be met if one processor is permitted to seize the memory for the amount of time required to perform the TAS instruction. The solution is a hardware-assisted Test and Set function. A special hardware register was designed sich that whenever it is accessed with a read-type instruction, its most significant bit is set to "one" after its contents are sent to the processor....