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Schottky Gate Cross-Over

IP.com Disclosure Number: IPCOM000062527D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Harder, C: AUTHOR [+2]

Abstract

This article describes a Schottky gate arrangement that allows cross- overs of DC lines without requiring additional wiring levels. This is achieved by using a parasitic reverse-biased FET as insulation between the lines, one being formed by the gate metallization, the second by an n+ implant. The invention permits a reduction in the area used for wiring, thus resulting in compact circuit designs. The figure illustrates the arrangement of the Schottky cross- over. The gate line is the first conductor, and the channel is the second conductor. Both are separated from each other by a Schottky barrier, provided this parasitic FET is reverse biased.

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Schottky Gate Cross-Over

This article describes a Schottky gate arrangement that allows cross- overs of DC lines without requiring additional wiring levels. This is achieved by using a parasitic reverse-biased FET as insulation between the lines, one being formed by the gate metallization, the second by an n+ implant. The invention permits a reduction in the area used for wiring, thus resulting in compact circuit designs. The figure illustrates the arrangement of the Schottky cross- over. The gate line is the first conductor, and the channel is the second conductor. Both are separated from each other by a Schottky barrier, provided this parasitic FET is reverse biased. The Schottky gate has a relatively large capacitance and exhibits some leakage current but is, nevertheless, very well suited for certain applications, particularly for cross-overs of power supply lines where only DC voltages are applied and where the leakage current is neglectable since it is small compared to the main current.

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