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Browse Prior Art Database

Bus Charge Level Control Circuit

IP.com Disclosure Number: IPCOM000062529D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR [+2]

Abstract

This article relates generally to VLSI (very large-scale integration) chip design and, more particularly, to data transfer among a plurality of macros along a common bus. A data bus common to a plurality of macros can be used during data transfer by employing active pull-up or pull-down devices to precharge and to maintain subsequent bus data charge. Referring to Fig. 1, macros 1 and 2, among a plurality, are connected to common bus 3 which is, in turn, connected to pull-up and pull-down devices within the broken line 4. Data transfer to and from the bus requires three clock phases: Phase PRE, Phase Out and Phase In. During Phase PRE, transistor 5 is turned on at its gate to precharge the bus to Vdd, since it is difficult for the macros to drive the whole bus up.

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Bus Charge Level Control Circuit

This article relates generally to VLSI (very large-scale integration) chip design and, more particularly, to data transfer among a plurality of macros along a common bus. A data bus common to a plurality of macros can be used during data transfer by employing active pull-up or pull-down devices to precharge and to maintain subsequent bus data charge. Referring to Fig. 1, macros 1 and 2, among a plurality, are connected to common bus 3 which is, in turn, connected to pull-up and pull-down devices within the broken line 4. Data transfer to and from the bus requires three clock phases: Phase PRE, Phase Out and Phase In. During Phase PRE, transistor 5 is turned on at its gate to precharge the bus to Vdd, since it is difficult for the macros to drive the whole bus up. During Phase Out the output transfer gate of the source, macro 1, turns on to transmit data onto the bus, pulling the precharged bus low if the output bit is 0 and maintaining the bus high if the bit is 1. Transistors 6 and 7 are off, thus isolating the bus and permitting macro 1 to set the proper bus level. During writing into the destination, macro 2, at Phase In, the bus level is maintained even if this macro sinks DC current. The gate voltage of push-pull drivers 6 and 7 is set by the bus level. If the bus is high from Phase Out, transistor 8 is on, forcing transistor 7 off even though Phase In may try to pull node B high through capacitor 9. The gate voltage of trans...