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Alternate Bus Master Tie Breaker Circuit

IP.com Disclosure Number: IPCOM000062531D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Buckton, WL: AUTHOR [+2]

Abstract

When a microprocessor is used as an alternate bus master for a microcomputer, a hang condition may exist if the microcomputer attempts to access the alternate bus master microprocessor at the same time that the alternate bus master microprocessor is attempting to access the microcomputer storage. The circuit shown in the figure causes the microprocessor to enter a retry operation during the contention condition thus allowing the microcomputer to complete its cycle without the need for software interlocks. Description of Contention Tie Breaker 1. The microprocessor 12 attempts to access the microcomputer system bus. The microprocessor 12 places its address on the bidirectional address bus 14 and address decoder 16 (#1) activates a bus request on line 18 to the host (not shown). 2.

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Alternate Bus Master Tie Breaker Circuit

When a microprocessor is used as an alternate bus master for a microcomputer, a hang condition may exist if the microcomputer attempts to access the alternate bus master microprocessor at the same time that the alternate bus master microprocessor is attempting to access the microcomputer storage. The circuit shown in the figure causes the microprocessor to enter a retry operation during the contention condition thus allowing the microcomputer to complete its cycle without the need for software interlocks. Description of Contention Tie Breaker 1. The microprocessor 12 attempts to access the microcomputer system bus. The microprocessor 12 places its address on the bidirectional address bus 14 and address decoder 16 (#1) activates a bus request on line 18 to the host (not shown). 2. Simultaneously with Step 1, the host is attempting to access the random-access memory (RAM) 20. The address decoder 22 (#2) senses the address and activates a bus request on line 24 to microprocessor 12. At this point, both processors are trying to access the other's RAM and each is waiting for the other to respond. 3. Logic 26 (#1) senses the presence of the above condition, synchronizes the host request to microprocessor 12, and generates a bus error on line 28 and halt to the microprocessor 12 which causes a bus retry operation. Microprocessor 12 relinquishes the bus to the host. When the host has finished its operation, the microprocessor 12 n...