Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Shift Register in MTL Using Injector Switching

IP.com Disclosure Number: IPCOM000062534D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Chesters, MJ: AUTHOR [+2]

Abstract

A four-phase shift register in merged transistor logic (MTL) with four gates per stage using injector switching is disclosed. The shift register is bidirectional and can be stopped and then reversed by reversing the sequence of the clock pulses. The shift register can be loaded and read out in parallel mode for parallel operation. A description of shift register operation follows with reference to the Fig. 1 circuit which shows a four-phase clock driving level sensitive latches and the Fig. 2 clock sequence. The MTL gates are twin injector types with up to four-gate inputs available. Serial Transfer Gates T1, T2, T3, T4 form a shift register stage. T0 and T5 have been added to show the method of interstage connection. The I/O pairs of lines are for parallel operation to be described later.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Shift Register in MTL Using Injector Switching

A four-phase shift register in merged transistor logic (MTL) with four gates per stage using injector switching is disclosed. The shift register is bidirectional and can be stopped and then reversed by reversing the sequence of the clock pulses. The shift register can be loaded and read out in parallel mode for parallel operation. A description of shift register operation follows with reference to the Fig. 1 circuit which shows a four-phase clock driving level sensitive latches and the Fig. 2 clock sequence. The MTL gates are twin injector types with up to four-gate inputs available. Serial Transfer Gates T1, T2, T3, T4 form a shift register stage. T0 and T5 have been added to show the method of interstage connection. The I/O pairs of lines are for parallel operation to be described later. Let clock D be active and T0 output be at '1'. T0/T1 form a latch pair (as also do T4/T5). T1 output is therefore '0'. This is the rest state between bit transfers. Latch pairs T0/T1 and T4/T5 hold bit data for successive bits in a data train.

(Image Omitted)

Clock A becomes active. T1 is already active, being powered also from clock D, but clock A also activates T2. Since T1 output is '0', then T2 output becomes 1. T2 base current being bypassed into T1 collector. T1/T2 form a latch pair. Clock D is deactivated, turning off T0. Clock B becomes active, having no effect on T2 but energizing T3 forming a latch pair with T2. Clock A activates turning off T1. Clock C energizes T4, and T3/T4 form a latch pair. Clock B becomes inactive, turning off T2. Clock D becomes active to make T4/T5 a latch pair. Clock C deactivates, turn...