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Tapered Sidewall Field-Effect Transistor Gates

IP.com Disclosure Number: IPCOM000062548D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Hoh, PD: AUTHOR [+2]

Abstract

In processing where implantation steps require abrupt sidewalls for definition but the abruptness introduces metallization difficulty, the sidewalls can be tapered by conformal film deposition followed by anisotropic etching. The technique is illustrated in Figs. 1-4 where PECVD is plasma enhanced chemical vapor deposition and the material is one of Si3N4, SiO2, and oxynitride. RIE is reactive ion etch. A 45Œ-50Œ sidewall is formed on the WSi gate.

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Tapered Sidewall Field-Effect Transistor Gates

In processing where implantation steps require abrupt sidewalls for definition but the abruptness introduces metallization difficulty, the sidewalls can be tapered by conformal film deposition followed by anisotropic etching. The technique is illustrated in Figs. 1-4 where PECVD is plasma enhanced chemical vapor deposition and the material is one of Si3N4, SiO2, and oxynitride. RIE is reactive ion etch. A 45OE-50OE sidewall is formed on the WSi gate.

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