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Method for Maintaining Multiple Timeout Counters

IP.com Disclosure Number: IPCOM000062576D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Brantley, WC: AUTHOR [+3]

Abstract

A method is described for maintaining timeout counters for requests transmitted over an interconnection network of a parallel processing system. The method minimizes the amount of hardware necessary to support the timeout counters. An extension of the method provides a technique for logging the latency of the request for performance monitoring. In order to maintain a high degree of performance in a parallel processing environment, a processing element (PE) and its associated hardware (such as a cache) must be able to have several unacknowledged loads and stores to memory concurrently outstanding. Since these requests are transmitted over an interconnection network that could potentially misroute a request, a timeout counter is necessary for each outstanding request.

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Method for Maintaining Multiple Timeout Counters

A method is described for maintaining timeout counters for requests transmitted over an interconnection network of a parallel processing system. The method minimizes the amount of hardware necessary to support the timeout counters. An extension of the method provides a technique for logging the latency of the request for performance monitoring. In order to maintain a high degree of performance in a parallel processing environment, a processing element (PE) and its associated hardware (such as a cache) must be able to have several unacknowledged loads and stores to memory concurrently outstanding. Since these requests are transmitted over an interconnection network that could potentially misroute a request, a timeout counter is necessary for each outstanding request. These timeout counters can simply be manifested as binary counters, one per request. If the total potential latency of a request is large and the number of concurrent outstanding requests is large, the amount of hardware necessary to maintain the timeout counters may be prohibitive. The following method drastically reduces the total hardware required. Instead of maintaining a full counter for each outstanding request, a single time-stamp counter is used plus a three-bit register for each outstanding request. The register bits are called: valid, count, and change. The valid bit indicates that the other two bits are valid. The count bit is the value of the most significant bit (MSB) of the time-stamp counter at the time the request was issued. T...