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Phase-Locked Loop Clock Recovery Circuit

IP.com Disclosure Number: IPCOM000062589D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Ewen, JF: AUTHOR [+2]

Abstract

The integration of a high speed clock recovery circuit onto a single chip is facilitated by using two phase-locked loops, one locked to a reference and the other locked to the data signal. A voltage-controlled oscillator (VCO) control bias from a reference loop (PLL) is summed and applied to a second VCO through a suitable control circuit. The net result is to control the VCO free-running frequency relative to a stable crystal reference frequency with an accuracy that is determined by the tracking between the oscillators inherent in a single chip, integrated approach. The tracking between the two VCOs is determined by the particular type of oscillator circuit chosen and by the control circuitry used to bias the two oscillators.

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Phase-Locked Loop Clock Recovery Circuit

The integration of a high speed clock recovery circuit onto a single chip is facilitated by using two phase-locked loops, one locked to a reference and the other locked to the data signal. A voltage-controlled oscillator (VCO) control bias from a reference loop (PLL) is summed and applied to a second VCO through a suitable control circuit. The net result is to control the VCO free-running frequency relative to a stable crystal reference frequency with an accuracy that is determined by the tracking between the oscillators inherent in a single chip, integrated approach. The tracking between the two VCOs is determined by the particular type of oscillator circuit chosen and by the control circuitry used to bias the two oscillators. A control circuit is provided giving suitable tracking between the two VCOs and allows for the gain of the oscillators to be individually adjusted for optimum performance. A principle is provided for controlling two VCOs in a dual PLL clock recovery arrangement which incorporates the adjustment of the VCO gain by controlling a subset of the total number of stages in the ring oscillator, the control of both the first oscillator and a subset of the second oscillator by the first PLL directly for improved tracking, and the use of a third VCO to equalize the loading of the output drivers for improved tracking performance. The principle is implemented through the control of a particular type of VCO implemented as a ring oscillator. Such a ring oscillator differs from an astable multivibrator oscillator in two respects: 1) the oscillator gain is very large, and 2) the gain is easily adjustable. For purposes of illustration, the oscillator gain is approximately 4 GHz/V or about 10 times greater than other oscillator types at similar frequencies. The advantage of a large gain is the reduction of the static phase error in the PLL, giving improved performance of the clock recovery circuit. Fig. 1 schematically illustrates a VCO, and Fig. 2 schematically illustrates a block diagram of the summing circuit. Care must be taken to insure accurate tracking between the two oscillators of the dual PLL. The technique consists of three parts. First, the gain of the VCO2 is adjusted to the optimum value for the PLL by controlling some subset of the total number of stages in the ring oscillator. Second, the remaining stages in VCO2 are controlled directly by the first PLL to improve the tracking performance. Finally, a third VCO is used to present a balanced load to all of the buffers in the summing circuit and further improves the tracking performance.

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Fig. 1 illustrates the technique used to control the VCO gain. The ring oscillat...