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Use of Process Synchronization Lines for Data Strobe and Acknowledge Signals

IP.com Disclosure Number: IPCOM000062592D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Taub, DM: AUTHOR

Abstract

The scheme described in this article overcomes the problem of inappropriate status information in IEEE P896 bus systems which include cache stores, and reduces the number of handshaking lines in the data-transfer portion of the bus from six to five. The proposed IEEE P896 multimicroprocessor bus is an asynchronous bus in which addresses and data are time-multiplexed on the same set of lines. It uses a total of six lines for 'handshaking', i.e., for indicating: a)when addresses and data presented on the bus are valid, and b) when they have been accepted by the recipient. The relevant protocols are described in P. Borrill and J.

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Use of Process Synchronization Lines for Data Strobe and Acknowledge Signals

The scheme described in this article overcomes the problem of inappropriate status information in IEEE P896 bus systems which include cache stores, and reduces the number of handshaking lines in the data-transfer portion of the bus from six to five. The proposed IEEE P896 multimicroprocessor bus is an asynchronous bus in which addresses and data are time-multiplexed on the same set of lines. It uses a total of six lines for 'handshaking', i.e., for indicating:
a)when addresses and data presented on the bus are valid, and b) when they have been accepted by the recipient. The relevant protocols are described in P. Borrill and J. Theus, "An advanced communication protocol for the proposed IEEE 896 Futurebus," published in IEEE Micro 4, 42-56 (August 1984); they are described also in the relevant Draft Specifications published by the IEEE Computer Society. This scheme suffers from a drawback in systems containing cache stores. Suppose that a master addresses a storage module in order to read a block of data, but that the cache in another module contains a more up-to-date version of the data. There is an arrangement by which this second module, called the intervening module, can prevent the addressed module from supplying the data, and can supply the data in its stead. However, both modules will supply status information on the same set of lines, ST3 to ST0, and so the master will receive the OR- function of the status supplied by each of them, without being able to tell which information came from which module. The scheme described here overcomes the above drawback and at the same time reduces the number of handshake lines from six to five. The six handshake lines in use at present are AS, AK, AI, DS, DK and DI. In the proposed scheme DS is retained with its function unchanged, but the other five lines are replaced by TP, TQ, TR and TS. These lines are used to synchronize a cycle of four operations in a way similar to that in which three lines can synchronize a cycle of three operations. The 3-line arrangement is described by D. M. Taub in "Arbitration and control acquisition in the proposed IEEE 896 Futurebus," published in IEEE Micro 4, 28-41 (August 1984). In the present scheme, the binary variables that individual modules apply to lines TP, TQ, TR, TS and DS are denoted respectively by tp, tq, tr, ts and ds. The lines are wired-OR lines in which binary 1 is represented by the less positive level; thus TP carries the OR- function of the tp variables applied by the individual modules, and similarly for the other lines. In the explanation that follows, a variable is said to be 'asserted' when it has the value binary 1, and 'released' when it has the value binary 0. Initially tp, tq, tr, ts and ds in all modules have the values 0, 0, 1, 1, 0, respectively, and so t...