Browse Prior Art Database

Cascode Voltage Switch for Cmos Logic

IP.com Disclosure Number: IPCOM000062593D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Hanafi, HI: AUTHOR [+2]

Abstract

This article relates generally to logic circuit switching and, more particularly, to improving switching speed by separation of the logic tree from its output nodes. Retention time, soft error exposure, race conditions and noise sensitivity can be alleviated in cascode logic switching by using a depletion device with grounded gate to isolate the output node from the tree branches. Referring to Fig. 1, T1 and T2 are p-channel devices and T3, T4, TA and TAN are n-channel devices. Assume all inputs to branches A and B of the logic tree are at high potential VH except devices TA and TAN whose inputs are controlled by signals SA and SAN, respectively. If input SA is low, node C is at VH, node B is at -VTD, where VTD is the depletion device threshold, and node CN is at ground. Thus, devices T1 and T2 are, respectively, on and off.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 96% of the total text.

Page 1 of 2

Cascode Voltage Switch for Cmos Logic

This article relates generally to logic circuit switching and, more particularly, to improving switching speed by separation of the logic tree from its output nodes. Retention time, soft error exposure, race conditions and noise sensitivity can be alleviated in cascode logic switching by using a depletion device with grounded gate to isolate the output node from the tree branches. Referring to Fig. 1, T1 and T2 are p-channel devices and T3, T4, TA and TAN are n-channel devices. Assume all inputs to branches A and B of the logic tree are at high potential VH except devices TA and TAN whose inputs are controlled by signals SA and SAN, respectively. If input SA is low, node C is at VH, node B is at -VTD, where VTD is the depletion device threshold, and node CN is at ground. Thus, devices T1 and T2 are, respectively, on and off. When input SA rises to VH, node

(Image Omitted)

B and hence, node C discharge toward ground, turning T2 on. This action pulls nodes CN and BN toward VH. When node BN reaches -VTD, device T3 turns off, isolating the tree branch B capacitance from the output node. Node CN then rises faster toward VH. Further performance improvement can be realized by connecting the gate of the p-channel devices T1 and T2, respectively, to nodes BN and B, as shown in Fig. 2. However, this arrangement has the disadvantage of DC current flow because nodes BN and B do not rise high enough to turn off the p-channel devices.

1

Pa...