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High Speed Bipolar Push-Pull Circuit

IP.com Disclosure Number: IPCOM000062603D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Wiedmann, SK: AUTHOR

Abstract

This article relates generally to VLSI charge-buffered logic circuits and, more particularly, to such circuits using bipolar devices. A bipolar push-pull output stage for charge-buffered logic can permit high speed operation and low power dissipation even with relatively poor switching characteristics. This circuit is also compatible with other standard logic circuits to improve switching speed and power dissipation at large capacitive loads. Referring to Fig. 1, PNP transistor T1 and NPN transistors T2, T3 and T4 are arranged as the output stage of a NAND circuit to large capacitive load 5. NPN emitter follower T2 quickly provides large currents to charge load 5 to speed up the upward output transition even (Image Omitted) if T1 has a lower cut-off frequency.

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High Speed Bipolar Push-Pull Circuit

This article relates generally to VLSI charge-buffered logic circuits and, more particularly, to such circuits using bipolar devices. A bipolar push-pull output stage for charge-buffered logic can permit high speed operation and low power dissipation even with relatively poor switching characteristics. This circuit is also compatible with other standard logic circuits to improve switching speed and power dissipation at large capacitive loads. Referring to Fig. 1, PNP transistor T1 and NPN transistors T2, T3 and T4 are arranged as the output stage of a NAND circuit to large capacitive load 5. NPN emitter follower T2 quickly provides large currents to charge load 5 to speed up the upward output transition even

(Image Omitted)

if T1 has a lower cut-off frequency. NPN transistor T3, in parallel with NPN transistor T4 at base and emitter terminals, provides an active fast pull-down of node A when T1 is turned off and T4 is turned on. This avoids simultaneous conduction of T2 and T4 and speeds up the output level change during down transitions. Large transient currents through T2 and T3 are avoided and no DC power is required. Transistor T3 preferably has a high inverse current gain to control current hogging between T3 and T4 if no saturation control is applied. Diode DL shifts the voltage level of the base of T1 to compensate for the base- emitter voltage shift caused by T2. Minimization of charge storage in transistors T3 and T4 can be obtained in Fig. 2 by clamp...