Browse Prior Art Database

Use of Constellation in VLSI Global Wire Routing

IP.com Disclosure Number: IPCOM000062606D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Cagle, JW: AUTHOR [+3]

Abstract

A method of grouping similar nets into groups called constellations simplifies and accelerates global wire routing approximately 10 times. Wire routing in hierarchical VLSI designs involves thousands of nets. A method is described for grouping these nets into constellations to reduce the problem by 10 times with no loss of design freedom. Global wire routing in VLSI design involves thousands of nets when the design is broken into a hierarchy of global and macro wiring. An example is shown in Fig. 1. Considerable complexity and speed gains can be obtained by working with constellations instead of individual nets. A constellation is a group of nets which go to exactly the same set of blocks as shown in Fig. 2.

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Use of Constellation in VLSI Global Wire Routing

A method of grouping similar nets into groups called constellations simplifies and accelerates global wire routing approximately 10 times. Wire routing in hierarchical VLSI designs involves thousands of nets. A method is described for grouping these nets into constellations to reduce the problem by 10 times with no loss of design freedom. Global wire routing in VLSI design involves thousands of nets when the design is broken into a hierarchy of global and macro wiring. An example is shown in Fig. 1. Considerable complexity and speed gains can be obtained by working with constellations instead of individual nets. A constellation is a group of nets which go to exactly the same set of blocks as shown in Fig. 2. By definition, all nets in a constellation have identical routing requirements and can be processed as a group with no loss in flexibility. Minor exceptions are occasional performance critical nets which receive special handling anyway and large constellations which must be subdivided into multiple routes to avoid overflows. The leverage provided by constellations varies with the design. In two real VLSI designs having greater than 20,000 circuits, there were approximately 2000 global nets but only approximately 200 constellations of those nets.

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