Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Speed Enhancement Technique for Current Switch Circuits

IP.com Disclosure Number: IPCOM000062608D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Chan, YH: AUTHOR

Abstract

The circuit technique disclosed in this article employs the intrinsic device capacitance of an inverse transistor for effective speed enhancement of a current switch circuit. The disclosed technique is simple to implement, costs nothing in power, chip area or layout complexity, and can be readily applied to improve the speed-power products of most CSEF (current-switch emitter-follower) circuits. (Image Omitted) A conventional CSEF inverter circuit is shown in Fig. 1. Circuit delay is determined by two factors: 1) power level (i.e., Ic), and 2) device speed (i.e., Ft and b of the NPN transistors T1, T2, and T3). For a given device type and a fixed current level, an external capacitor C (see dotted line) is sometimes added to the common emitter node 2 to improve the AC performance of this design.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 60% of the total text.

Page 1 of 2

Speed Enhancement Technique for Current Switch Circuits

The circuit technique disclosed in this article employs the intrinsic device capacitance of an inverse transistor for effective speed enhancement of a current switch circuit. The disclosed technique is simple to implement, costs nothing in power, chip area or layout complexity, and can be readily applied to improve the speed-power products of most CSEF (current-switch emitter-follower) circuits.

(Image Omitted)

A conventional CSEF inverter circuit is shown in Fig. 1. Circuit delay is determined by two factors: 1) power level (i.e., Ic), and 2) device speed (i.e., Ft and b of the NPN transistors T1, T2, and T3). For a given device type and a fixed current level, an external capacitor C (see dotted line) is sometimes added to the common emitter node 2 to improve the AC performance of this design. The added capacitance aids in accelerating the rise and fall times seen at the node 1 during switching. The speed gain comes, however, at the cost of increased silicon area and layout complexity, not practical in VLSI design.

Fig. 2 shows the schematic of an improved CSEF circuit. It achieves faster switching speed at no additional cost in power, chip area or layout complexity. The design takes advantage of the inherent device capacitance (i.e., Ccb and Ccs) of an inverse NPN transistor for speed enhancement. The reference transistor T2, in the circuit of Fig. 2, is inverted so that it operates in the inverse mode whe...