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Three-Level Decoding Scheme for High Density Arrays

IP.com Disclosure Number: IPCOM000062626D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

A method has been proposed to reduce the area and power required by decoders of large arrays in semiconductor devices. It provides for emitter dotting of the true-complement generator outputs along with a matrix decode. (Image Omitted) For high density arrays it is common to use two-level decoding schemes. These include transistor-transistor logic (TTL) and emitter- coupled logic (ECL) decoders. This proposal suggests a three-level decoding scheme to further minimize the power, delay and area required for dense arrays (for example, cell count > 80 Kbits). _ The circuitry in Fig. 1 is for a low wordline down swing and for a relatively low input level. If higher levels are used, some ground voltage sources may be replaced with current sinks, as indicated in Fig. 2.

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Three-Level Decoding Scheme for High Density Arrays

A method has been proposed to reduce the area and power required by decoders of large arrays in semiconductor devices. It provides for emitter dotting of the true-complement generator outputs along with a matrix decode.

(Image Omitted)

For high density arrays it is common to use two-level decoding schemes. These include transistor-transistor logic (TTL) and emitter- coupled logic (ECL) decoders. This proposal suggests a three-level decoding scheme to further minimize the power, delay and area required for dense arrays (for example, cell count > 80 Kbits).

_ The circuitry in Fig. 1 is for a low wordline down swing and for a relatively low input level. If higher levels are used, some ground voltage sources may be replaced with current sinks, as indicated in Fig. 2. In both configurations, in standby the top 16 decoders are off with the output high; the bottom 16 decoders are on with the output low. In access the 15 unselected top decoders are turned on with the output down and the one selected bottom decoder is turned off with the output up. The first level logic is accomplished with emitter dotting; the second level with 2-way NOR gates; and the third with series gating. The main components to implement the 8-->256 decoding scheme are two groups of eight-bit bus, each line with a dot of 2 and fanout of 4, and two groups of 16 2-way NOR gates. In both Figs. 1 and 2, the clocking logic is similar to that of [*]. Th...