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Metal-Oxide-Semiconductor Cascode Mirror Circuit

IP.com Disclosure Number: IPCOM000062635D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Smith, MJ: AUTHOR

Abstract

A cascode mirror circuit of the type described by Choy et al entitled "High-Frequency CMOS Switched-Capacitor Filters for Communications Application" in the IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 6, p. 652 et seq, December 1983, is improved by the addition of series resistive impedance, as shown in Fig. 1. (Image Omitted) The circuit in Fig. 1 uses R1 and R2 to introduce negative feedback in order to increase the output impedance of QY. The back-gate bias effect on QX and QY increases their threshold voltages. The output characteristics of the circuit are shown in Figs. 2 and 3, and demonstrate a transfer ratio of 92%. The output impedance of the circuit is about 2.5 times higher than the standard mirror for similarly sized devices. This is due to the local negative feedback.

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Metal-Oxide-Semiconductor Cascode Mirror Circuit

A cascode mirror circuit of the type described by Choy et al entitled "High- Frequency CMOS Switched-Capacitor Filters for Communications Application" in the IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 6, p. 652 et seq, December 1983, is improved by the addition of series resistive impedance, as shown in Fig. 1.

(Image Omitted)

The circuit in Fig. 1 uses R1 and R2 to introduce negative feedback in order to increase the output impedance of QY. The back-gate bias effect on QX and QY increases their threshold voltages. The output characteristics of the circuit are shown in Figs. 2 and 3, and demonstrate a transfer ratio of 92%. The output impedance of the circuit is about 2.5 times higher than the standard mirror for similarly sized devices. This is due to the local negative feedback. The increase in output impedance is approximately 2.5 for the 80K resistor values shown, and the output impedance may be further increased by increasing the values of R1 and R2 at the expense of the mirror voltage burden. The voltage burden is the lowest voltage which can be placed across the mirror output before the output impedance starts to fall. In addition to flexibility in design, the circuit of Fig. 1 uses fewer devices, thus allowing potential savings in area.

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