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Converting an Engineering Changeable Substrate to Permanent Format

IP.com Disclosure Number: IPCOM000062644D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Arnold, AJ: AUTHOR [+3]

Abstract

A method has been proposed to improve the top surface of a multilayer ceramic (MLC) substrate after the engineering bring-up phase of the program. The proposal suggests the laminating and sintering of a through-via-layer which contains only those features required at the surface for interconnection with semiconductor devices. In the design of conventional MLC substrates the top surface contains features such as C4 pads for device joining and engineering change (EC) pads and laser delete lines for rewiring capability. After a certain point in the manufacturing cycle it is usually desirable to remove unnecessary top surface features. The conventional approach to removing unwanted features is to redesign the top layer as well as underlying redistribution layers so that unneeded features are not brought to the top surface.

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Converting an Engineering Changeable Substrate to Permanent Format

A method has been proposed to improve the top surface of a multilayer ceramic (MLC) substrate after the engineering bring-up phase of the program. The proposal suggests the laminating and sintering of a through-via-layer which contains only those features required at the surface for interconnection with semiconductor devices. In the design of conventional MLC substrates the top surface contains features such as C4 pads for device joining and engineering change (EC) pads and laser delete lines for rewiring capability. After a certain point in the manufacturing cycle it is usually desirable to remove unnecessary top surface features. The conventional approach to removing unwanted features is to redesign the top layer as well as underlying redistribution layers so that unneeded features are not brought to the top surface. Using the method proposed herein, the need for redesign is eliminated. The added through-via- layer herein proposed would contain only features unrelated to rewiring (C4 pads) for continuation above the original surface layer. All original circuit paths would be preserved, thereby eliminating any chance of error introduction or performance shifting.

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