Browse Prior Art Database

FIFO Register for Graphics Display

IP.com Disclosure Number: IPCOM000062654D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Taylor, JL: AUTHOR

Abstract

This disclosure relates to a graphics display, where the display buffer is operated in page mode and intermittent bursts of data must be queued for serialization. A fast first-in, first-out (FIFO) queue implemented in LSSD (level sensitive scan design) is described where data is removed from the output on a regular cycle to a serializer. A feature is a fast path from data-in to data-out which allows data to be presented to the FIFO as late as one clock cycle before it is required from the FIFO without causing an under-run. The FIFO register is implemented in LSSD as described in U.S. Patents 3,761,695, 3,783,254 and 3,784,907. A logic network designed within LSSD rules requires sequential logic controlled by two or more non-overlapping clock trains. Fig.

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FIFO Register for Graphics Display

This disclosure relates to a graphics display, where the display buffer is operated in page mode and intermittent bursts of data must be queued for serialization. A fast first-in, first-out (FIFO) queue implemented in LSSD (level sensitive scan design) is described where data is removed from the output on a regular cycle to a serializer. A feature is a fast path from data-in to data-out which allows data to be presented to the FIFO as late as one clock cycle before it is required from the FIFO without causing an under-run. The FIFO register is implemented in LSSD as described in U.S. Patents 3,761,695, 3,783,254 and 3,784,907. A logic network designed within LSSD rules requires sequential logic controlled by two or more non-overlapping clock trains. Fig. 1 illustrates the FIFO register with clock inputs from control logic whose rules for clock generation are given in Fig. 2. The FIFO is a 64-bit-wide 8-stage register. An input from the depth register indicates how full the register is. The depth register is operated as a nine-state up/down counter. Depth designates the topmost

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valid word of data in FIFO, and so is zero when the FIFO is empty. The depth register is updated to reflect the amount of data held in the FIFO. The circuit is operated with multiple clocks under LSSD rules. All inputs are sampled at C- clock time and appropriate A, B and C- clocks are generated. A clock ring counts states 0, 2, 4 and 6 on...