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Substrate With Top Surface Metallurgy Adapted for Mixed Technology Device Bonding and Processing

IP.com Disclosure Number: IPCOM000062673D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Phelps, DW: AUTHOR [+3]

Abstract

This technique provides electrical connection terminals on a substrate for the attachment of both solder joined flip-chip semiconductor devices and back-bonded exposed-face wire-bond devices on the same substrate. The wire bonds are monometallic aluminum and isolated from the solder metals, allowing this combination to coexist even under the extreme temperatures (375ŒC) required to chip back-bond or solder attach or repair flip-chip devices, as can be required on multi-chip modules and without exposure of solder pots to aluminum contamination during tinning.

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Substrate With Top Surface Metallurgy Adapted for Mixed Technology Device Bonding and Processing

This technique provides electrical connection terminals on a substrate for the attachment of both solder joined flip-chip semiconductor devices and back- bonded exposed-face wire-bond devices on the same substrate. The wire bonds are monometallic aluminum and isolated from the solder metals, allowing this combination to coexist even under the extreme temperatures (375OEC) required to chip back-bond or solder attach or repair flip-chip devices, as can be required on multi-chip modules and without exposure of solder pots to aluminum contamination during tinning. In this process, the top surface metallurgy of the substrate is formed by standard evaporation techniques through deposition of blanket layers of chromium, copper, and chromium followed by photochemical and etch processes to produce personalized surface circuit metal patterns for the various devices. Wherever tinning of the surface pattern is required, such as at the fingers for flip-chip or at "donuts" for connection to module pins, the surface chromium is etched to expose the copper layer followed by pinning and tinning. At this point, the substrate will accept assembly and soldering of flip-chip devices but will not accommodate wire bonding of non flip-chip devices because neither the tinned copper nor chromium surfaces are metallurgically compatible with any known conventional wire-bond material or process....