Browse Prior Art Database

Alteration of Threshold Voltage of Enhancement Field-Effect Transistors

IP.com Disclosure Number: IPCOM000062675D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

Abadeer, WW: AUTHOR [+2]

Abstract

Controlled amounts of trapped positive charge (holes) in standard SiO2 gate insulator alters threshold voltage (Vt) of enhancement field-effect transistors (FETs). By applying controlled amplitude current pulses while a gate insulator field exceeding a critical value (Ec = approximately 6 megavolts per centimeter) is applied, trapped charges are created in a controlled manner. The Vt of the device may be measured between current pulses to detect achievement of desired Vt level. A standard high Vt enhancement transistor can be operated as a low Vt, zero Vt, or depletion device by trapping appropriate charge levels. The figure shows the change in Vt of an enhancement transistor resulting from applying a series of 1 microamp current pulses while a field exceeding Ec is applied.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Alteration of Threshold Voltage of Enhancement Field-Effect Transistors

Controlled amounts of trapped positive charge (holes) in standard SiO2 gate insulator alters threshold voltage (Vt) of enhancement field-effect transistors (FETs). By applying controlled amplitude current pulses while a gate insulator field exceeding a critical value (Ec = approximately 6 megavolts per centimeter) is applied, trapped charges are created in a controlled manner. The Vt of the device may be measured between current pulses to detect achievement of desired Vt level. A standard high Vt enhancement transistor can be operated as a low Vt, zero Vt, or depletion device by trapping appropriate charge levels. The figure shows the change in Vt of an enhancement transistor resulting from applying a series of 1 microamp current pulses while a field exceeding Ec is applied. The new Vt value resulting from the creation of trapped charge in the gate dielectric (SiO2) is measured between pulses. The charge per unit area (Charge/Area) trapped in the gate dielectric is plotted on the horizontal axis. A transistor, having been pulsed to any given Vt, is stable for several hundred hours of operation under normal operating temperature and may be reset very reproducibly. There is no degradation in device subthreshold leakage slope or transconductance.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]