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Multi-Port Latch-Trigger SRL Circuit With Automatic Reload Feature

IP.com Disclosure Number: IPCOM000062684D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Ng, SK: AUTHOR [+2]

Abstract

A circuit is provided that compensates for late system clock arrival in a multi-port shift register latch (SRL). As seen in Fig. 1, a typical logical implementation of a multi-port SRL has two polarity hold latches L1, L2, and a two port latch 1, 2. When the system clock (SC) is in a logical true state and the gate line for port 1 (G1) is activated, the input data (D1) becomes the content of the L1 latch until changed by the proper combination of inputs. Similarly, data port 2 can transfer data into L1 by activating SC and G2. The T line is used to transfer data from L1 to L2. Although Fig. 1 represents a two-port design, it can be generalized to an N port structure. The type of system clocking used in a latch-trigger design is seen in Fig. 2.

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Multi-Port Latch-Trigger SRL Circuit With Automatic Reload Feature

A circuit is provided that compensates for late system clock arrival in a multi- port shift register latch (SRL). As seen in Fig. 1, a typical logical implementation of a multi-port SRL has two polarity hold latches L1, L2, and a two port latch 1, 2. When the system clock (SC) is in a logical true state and the gate line for port 1 (G1) is activated, the input data (D1) becomes the content of the L1 latch until changed by the proper combination of inputs. Similarly, data port 2 can transfer data into L1 by activating SC and G2. The T line is used to transfer data from L1 to L2. Although Fig. 1 represents a two-port design, it can be generalized to an N port structure. The type of system clocking used in a latch-trigger design is seen in Fig. 2.

(Image Omitted)

During the time when SC is active, the L1 portion of th SRL can be loaded with data from any of its ports. Whether it is loaded or not depends on the logical state of each port's gate line. Ideally, the gate line should overlap the SC clock time. During the time the trigger clock T is active the contents of the L1 portion of the SRL is transferred into the L2 component of the structure. SC and T can be slightly overlapped or mutually exclusive. Typically, the L2 latches feed combinatorial logic which in turn feeds L1 latches of other SRLs. L1's only feed their associated L2's. Ideally, the gate lines should be mutually exclusive and active for the entire SC time. When performance is maximized, however, this is usually not the case. Since the gate lines are usually a product of combinatorial lines and subject to multiple levels of logic delays,

(Image Omitted)

they can and often do not get resolved well into the SC clocking period. This presents no problem if the final value of the gate lines results in only one gate being active by the end of the system clock period (minus latch set-up time). However, a problem exists when a gate line is active during a portion of the system clock time and becomes inactive before the end of the SC pulse (Fig. 3). In this case, the latch is loaded by the data associated with this particular gate line; the desired result is, however, that the L1 remain in its previous state (same as the L2), and during the T clock period, the erroneous data will be transferred to its associ...