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Hardware Cache Simulator for Desktop S/370

IP.com Disclosure Number: IPCOM000062695D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Erhard, JJ: AUTHOR [+5]

Abstract

One method of increasing performance on mainframe and minicomputers has been to implement a cache memory as a small, high speed memory array between the processor and slower main memory. As the demand for desk- top processing power increases, the addition of a cache memory to microprocessor-based workstations, such as the Personal Computer AT/ 370, becomes attractive. Traditionally, software simulation has been employed to quantify the performance gain provided by using a cache memory. One alternative that retains the versatility of a software simulation model, yet provides a more accurate measurement of the increase in system throughput, is a general-purpose Hardware Cache Simulator. A Hardware Cache Simulator can simulate many different sizes of cache memory, varying in both width and number of entries.

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Hardware Cache Simulator for Desktop S/370

One method of increasing performance on mainframe and minicomputers has been to implement a cache memory as a small, high speed memory array between the processor and slower main memory. As the demand for desk- top processing power increases, the addition of a cache memory to microprocessor- based workstations, such as the Personal Computer AT/ 370, becomes attractive. Traditionally, software simulation has been employed to quantify the performance gain provided by using a cache memory. One alternative that retains the versatility of a software simulation model, yet provides a more accurate measurement of the increase in system throughput, is a general- purpose Hardware Cache Simulator. A Hardware Cache Simulator can simulate many different sizes of cache memory, varying in both width and number of entries. It can be configured to store specific types of memory accesses, e.g., instructions and/or data, Supervisor state and/or Problem state, and virtual address and/or real address. Any combination of these types can coexist in a Hardware Cache Simulator, allowing the size allocated to each selected type to change dynamically. To implement a Hardware Cache Simulator, it is necessary to store the same tag information as in the potential cache memory, including address bits and other bits which differentiate between various types of accesses (e.g., virtual vs. real). A data valid bit must also be included, but the data itself need not be stored. The processor address bus and tag bits would be externally monitored, preventing the...