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Hazard-Free L1 Latch Design to Reduce the Cell and Connection Count for the a Clock Distribution

IP.com Disclosure Number: IPCOM000062697D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Dick, CJ: AUTHOR [+2]

Abstract

Hazard-free latch designs which require multiple global connections to the extend ports for the clocks, in order to optimize the cell count of the latch book, are connection limited rather than cell limited. A latch design which requires no additional latch cell area and reduces the number of control lines required by the extend port is described below. This design modifies the means by which the A clock (used only during scan operation) is generated and used in a logically hazard-free latch. The actual latch performance and operation during normal system operation is unaffected by this new design except for second-order effects of reduced overall cell count and improved wireability. (Image Omitted) As seen in Fig. 1, a clock driver (blocks 11 and 12) generates plus and minus phases of the A clock.

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Hazard-Free L1 Latch Design to Reduce the Cell and Connection Count for the a Clock Distribution

Hazard-free latch designs which require multiple global connections to the extend ports for the clocks, in order to optimize the cell count of the latch book, are connection limited rather than cell limited. A latch design which requires no additional latch cell area and reduces the number of control lines required by the extend port is described below. This design modifies the means by which the A clock (used only during scan operation) is generated and used in a logically hazard-free latch. The actual latch performance and operation during normal system operation is unaffected by this new design except for second-order effects of reduced overall cell count and improved wireability.

(Image Omitted)

As seen in Fig. 1, a clock driver (blocks 11 and 12) generates plus and minus phases of the A clock. The +A clock gates the scan input block 18 while the -A clock degates the data and extend ports (blocks 14 and 15) and latch block 17. During normal system the +C clock (output of block 13) gates the data and extend blocks. Therefore, the extend blocks need two globally wired control inputs (-A coming from the same clock driver as that driving the latch and +C coming from the latch itself). The A clock driver sees one load per latch on the +A phase and two loads per latch plus one load per extend on the -A phase. Because the -A phase must already drive the +A phase, the tot...