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Chemical Vapor Deposition of Tungsten to Fill Oversize Vias

IP.com Disclosure Number: IPCOM000062698D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Cronin, JE: AUTHOR

Abstract

A technique is shown for filling various contact hole sizes while at the same time optimizing the electrical properties of the film. Chemical vapor deposition (CVD) contact metal thickness is controlled as a function of the electrical properties, such as resistance and capacitance, required by the given design. Filling various size contact holes is a concern in certain designs, where contacts may carry varying amounts of current or require low contact resistance. Contact hole size must be independent of film thickness for all VLSI technologies to avoid performance degradation. Three different size contact holes are shown in Fig. 1. A hole having a width less than X, and a hole having a width of X, is filled by a CVD metal having a thickness of one-half X. A hole having a width greater than X is not filled during this step.

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Chemical Vapor Deposition of Tungsten to Fill Oversize Vias

A technique is shown for filling various contact hole sizes while at the same time optimizing the electrical properties of the film. Chemical vapor deposition (CVD) contact metal thickness is controlled as a function of the electrical properties, such as resistance and capacitance, required by the given design. Filling various size contact holes is a concern in certain designs, where contacts may carry varying amounts of current or require low contact resistance. Contact hole size must be independent of film thickness for all VLSI technologies to avoid performance degradation. Three different size contact holes are shown in Fig. 1. A hole having a width less than X, and a hole having a width of X, is filled by a CVD metal having a thickness of one-half X. A hole having a width greater than X is not filled during this step. Thus, subsequent process steps, such as masking, etching or passivation, may encounter problems with such a void. The dotted lines show CVD film growth from the semiconductor surfaces at time T1, T2 and Tn. A planarization process flow which will fill oversize holes and also allow for optimization of electrical parameters is shown in Fig. 2. The process involves iterative steps of tungsten (W) vapor deposition, partial etchback, deposition, partial etchback, etc., in order to planarize large holes and end up with a final film thickness as required by the design parameters. The etchback...